1. Field of the Invention
The present invention and a manufacturing method thereof relates to a semiconductor device having a polish preventing pattern. More particularly, the present invention relates to a semiconductor device having a polish preventing pattern for preventing an end of an element formation region to be shaved when an interlayer oxide film is planalized by the CMP method in a subsequent process because the element formation region formed by trench isolation at a surface of a semiconductor substrate is arranged so as to be isolated horizontally from other element formation regions.
2. Description of the Background Art
The LOCOS (LOCal Oxidation of Silicon) method for forming an isolation oxide film, which has a uniform film thickness, near a surface of a semiconductor substrate by thermally oxidizing a silicon substrate has been employed as a means of forming an element isolation region for isolating an element formation region of the semiconductor device. The LOCOS method has been an effective means of isolating an element formation regions in conventional semiconductor devices with a relatively lower degree of integration.
However, in the LOCOS method, a bird""s beak is formed, which is thermal oxidation at an end of an element formation region along a main surface of a semiconductor substrate. When the LOCOS method is used for a semiconductor device in which small element formation regions are formed, the bird""s beak may oxidize all of the element formation regions. Accordingly, the element formation regions may be lost, and therefore the LOCOS method cannot be applied to highly integrated semiconductor devices.
As a means of isolating an element formation region as an alternative to the LOCOS method, the trench isolation method in which an insulation film is filled in a trench that is provided in a silicon substrate has been used. In the trench isolation method, a silicon substrate is first shaved by anisotropic etching to form a trench to a prescribed depth from the main surface of the silicon substrate. An insulation film such as an oxide film is then filled in the trench to such an extent that the insulation film slightly rises from the main surface of the silicon substrate. Thereafter, the insulation film is polished to such an extent that the insulation film surface approaches the main surface of the silicon substrate. Thus, the main surface of the insulation film is planarized while the surface of the element formation region is exposed. An element isolation region is formed in this manner.
As a method of planalizing the insulation film surface, the CMP (Chemical Mechanical Polishing) method in which an isolation insulation film is filled and thereafter the entire surfaces of the silicon substrate and the isolation insulation film are chemically and mechanically polished is used. In the CMP method, the entire surfaces of a silicon substrate and an isolation insulation film are polished by introducing a polishing liquid on the surfaces of the silicon substrate and the isolation oxide film and rotating the silicon substrate while pressing a polishing cloth against the entire surfaces of the silicon substrate and the isolation insulation film.
The CMP method is characterized in that a protruding portion of a silicon substrate is polished first. When such a portion as an element formation region that is not to be polished protrudes, a protection film such as a nitride film is generally provided on its surface to prevent polishing of the protruded portion.
However, the polishing speed of an oxide film is considerably higher than that of a nitride film. Thus, the following problems occur in the CMP method polishing. Referring to FIGS. 38-48, typical problems with the CMP method polishing will be described in the following.
In the CMP method polishing, as can be seen from the states before and after polishing shown in FIGS. 38 and 39, the proportion of area in which nitride films 112a, 112b, 112c, 112d, 112e, 112f are distributed and the proportion of area in which oxide films 114a, 114b, 114c, 114d, 114e are distributed are greatly different between regions that have a high density of element formation regions, that is, a region between element formation regions 102a and 102b, a region between element formation regions 102b and 102c, a region between element formation regions 102d and 102e, a region between element formation regions 102e and 102f, and a region that has a low density of element formation regions, that is, a region between element formation regions 102c and 102d. Accordingly, a region having a large area proportion of nitride films is hardly shaved and keeps a planar surface while a region having a larger area proportion of oxide films is easily shaved and shaved to a greater extent toward its center. Thus, a dent d1 is created as shown in FIG. 39. Dent d1 affects formation of an aluminum interconnection and the like that are provided on oxide film 114c in a subsequent process.
As shown in FIG. 40, in the process of forming oxide film 114 to cover element formation regions 102a, 102b, the oxide film is deposited to the shape of protruding element formation regions 102a, 102b. Accordingly, the surface is roughened and have considerably large rise and falls as a whole. In order to etch the entire particularly protruded portion of oxide film 114, a slightly dented portion of oxide film 114 may slightly be excessively etched. When the oxide film is successively etched from the state of FIG. 40 to the states of FIGS. 41, 42, 43 and 44, nitride film 112 on an end of element formation region 102a and nitride film 113 formed on small element formation region 102b, which are under slightly dented oxide film 114, locally receive large pressure from a polishing cloth. Accordingly, the etching speed of nitride film 112 on the end of element formation region 102a and nitride film 113 formed on small element formation region 102b increases compared with the etching speed of nitride films at other portions. Thus, nitride film 112 on the end of element formation region 102a and nitride film 113 formed on small element formation region 102b are greatly shaved compared with nitride films at other portions and lose their function as a protection film. As a result, the end of element formation region 102a and small element formation region 102b are disadvantageously polished as shown in FIG. 45.
In order to prevent lowering of the function of nitride films 112, 113 as a protection film, a method using a polish preventing pattern is utilized. Referring to FIGS. 46-48, the method will be described in the following.
In the process of forming element formation region 102 as shown in FIG. 46 on semiconductor substrate 101, element formation region 102 is formed on silicon substrate 101 and, at the same time, a trench is formed in semiconductor substrate 101 by using the same mask. By leaving the main surface, island-type polish preventing patterns 111 as dummy patterns are formed in an element isolation region to have the same size and regular intervals regardless of the position of element formation region 102 as shown in FIG. 47.
By using this method, the surface of silicon substrate 101 has nitride films almost uniformly distributed on the entire surface not only on element formation region 102 but on a portion to be an element isolation region. Since the entire surfaces of element formation region 102 and the element isolation region are polished at an almost uniform etching speed, nitride film 112 on the end of element formation region 102a and nitride film 113 formed on small element formation region 102b as shown in FIGS. 44 and 45 are prevented from being shaved to a greater extent than other portions and losing the function as a protection film.
However, the above described island-type polish preventing patterns 111 are formed in the same size and at regular intervals regardless of the shape, position and size of element formation region 102. Accordingly, a polishing cloth gets into a gap between element formation regions 102 and a large gap between an element formation region and polish preventing pattern 111, and therefore large pressure is applied to the portions. Accordingly, such a portion 150 of an element formation region that is on a line extended from a gap between polish preventing patterns 111 as well as an end 160 of an element formation region on the side of such a portion that has a larger gap than another because of the positional relationship between polish preventing patterns 111 and element formation region 102 are greatly etched. It can be considered that these disadvantageous phenomena are caused because small polish preventing patterns 111 are arranged in the same size and at regular intervals regardless of the position of element formation region 102.
The present invention was made to solve the above described problems, and its object is to provide a semiconductor device having a polish preventing pattern for improving the planarity of an element formation region by intentionally arranging the polish preventing pattern to the shape of the element formation region and thereby reducing the possibility that the element formation region is partially etched when an isolation oxide film in a trench isolation structure is planarized by the CMP method.
A semiconductor device of the present invention includes a polish preventing pattern surrounding an element formation region, formed at a main surface of a semiconductor device, in substantially a continuous manner at an almost uniform distance horizontally from the outer edge of the element formation region.
According to such a structure, the polish preventing pattern of the present invention continuously surrounds an element formation region, and therefore such a gap does not exist that corresponds to a gap between the island-type polish preventing patterns described in the prior art. Since the polish preventing pattern of the present invention is provided at a prescribed distance from the outer edge of an element formation region, there is not a difference in the space between the island-type polish preventing patterns and the outer edge of the element formation region due to the position of the element formation region. Accordingly, in the polishing step using a polishing cloth such as the CMP method, disadvantageous polishing of part of the element formation region outer edge is suppressed. As a result, the planarity of the main surface of an element formation region can be improved.
In the semiconductor device of the present invention, it is preferred that the polish preventing pattern includes a remainder of the main surface of a semiconductor substrate, which is adjacent to a trench provided around the element formation region, at the main surface of the semiconductor substrate.
According to such a structure, an element formation region and the polish preventing pattern can be formed to have the same height. Therefore, in the polishing step using a polishing cloth, the surface of an element formation region is prevented from being polished more reliably and an insulation film is polished completely. Since the polish preventing pattern can be formed simultaneously with formation of a trench for element isolation, the polish preventing pattern can be formed without increasing the manufacturing steps.
In the semiconductor device of the present invention, it is more preferred that an insulation film is filled in a trench between the outer edge of an element formation region and the polish preventing pattern.
According to such a structure, the trench between the outer edge of the element formation region and the polish preventing pattern functions as an element isolation region.
In the semiconductor device of the present invention, it is preferred that the polish preventing pattern is formed at a prescribed distance from a conductive layer.
According to such a structure, an element formation region and the conductive layer are prevented from being short-circuited through the polish preventing pattern.
In the semiconductor device of the present invention, it is preferred that the polish preventing pattern is formed at a prescribed distance from the boundary of an impurity diffusion region.
According to such a structure, a disadvantageous phenomenon such as latch up caused through the polish preventing pattern or deterioration of the isolation characteristics can be suppressed in the boundary of an impurity diffusion region.
In the semiconductor device of the present invention, it is preferred that the polish preventing pattern further includes a polish preventing pattern for well-potential fixation formed to horizontally surround a well and fixed in potential by another electrode to fix the well potential.
According to such a structure, the polish preventing pattern for well-potential fixation is provided, and therefore the polish preventing pattern has the effect of improving the planarity of an element formation region and the function of fixing the well potential.
In the semiconductor device of the present invention, it is preferred that the polish preventing pattern includes a loop-shaped polish preventing pattern extending in a band shape.
According to such a structure, good insulation characteristics between adjacent element formation regions are maintained by forming an insulation film between an element formation region and the loop-shaped polish preventing pattern and between the loop-shaped polish preventing pattern and another element formation region.
In the semiconductor device of the present invention, it is more preferred that the polish preventing pattern includes a concavity formation preventing pattern formed at a distance from the loop-shaped polish preventing pattern with an insulation film therebetween.
According to such a structure, the concavity formation preventing pattern exists at the center of an element isolation region when element formations are formed largely spaced apart. Therefore, excessive polishing of the center of the element isolation region is suppressed, and the planarity of the element isolation region is improved.
In the semiconductor device of the present invention, it is more preferred that a pad for receiving signals is further formed on the concavity formation preventing pattern.
According to such a structure, the electrode pad is positioned on the concavity formation preventing pattern away from an element formation region, and the electric adverse effects of the signal receiving pad on conductive regions such as other element formation regions can be reduced.
In the semiconductor device of the present invention, it is more preferred that the loop-shaped polish preventing pattern has a discontinuous portion.
According to such a structure, the loop-shaped polish preventing pattern has a discontinuous portion, and therefore a conductive layer can be formed in the discontinuous portion. Therefore, the loop-shaped polish preventing pattern can be prevented from coming into contact with the conductive layer and, at the same time, an element formation region surrounded by the loop-shaped polish preventing pattern can electrically be connected to another element formation region or the conductive layer.
When element formation regions and the loop-shaped polish preventing pattern are close to each other, the element formation regions are electrically connected through the loop-shaped polish preventing pattern, and therefore the isolation characteristics may be lowered.
In the semiconductor device of the present invention, however, the loop-shaped polish preventing pattern is divided into at least two portions when the loop-shaped polish preventing pattern has at least two discontinuous portions. Accordingly, at least two element formation regions can be surrounded by at least two portions of one loop-shaped polish preventing pattern. Since electric connection is disconnected by the discontinuous portions at this time, electric connection between element formation regions through the loop-shaped polish preventing pattern can be suppressed. As a result, the isolation characteristics of the element formation regions are improved.
In the semiconductor device of the present invention, it is preferred that the polish preventing pattern includes another loop-shaped polish preventing pattern outside the above described loop-shaped polish preventing pattern.
According to such a structure, by an arbitrary combination of patterns selected from the group of a loop-shaped polish preventing pattern not having a discontinuous portion and a loop-shaped polish preventing pattern having a discontinuous portion, the loop-shaped polish preventing pattern is at least doubly formed horizontally for one element formation region. Accordingly, the isolation characteristics between element formation regions are further improved.
Further, the outer loop-shaped polish preventing pattern suppresses polishing of the inner loop-shaped polish preventing pattern. Accordingly, the possibility that an end of an element formation region is polished in the polishing step using a polishing cloth is further reduced, and the planarity of an element formation region is further improved.
If the loop-shaped polish preventing patterns having a discontinuous portion are used, an element formation region surrounded by the loop-shaped polish preventing portions can electrically be connected to another element formation region or a conductive layer.
A method of manufacturing a semiconductor device of the present invention includes the steps of forming a trench to a prescribed depth from a main surface of a semiconductor substrate around an element formation region of the semiconductor substrate having the main surface thereby forming a polish preventing pattern having a remainder of the main surface to surround the element formation region in a substantially continuous manner at an almost uniform distance horizontally from the outer edge of the element formation region, forming an insulation film to cover the trench, the polish preventing pattern and the surface of the element formation region, and polishing and removing the insulation film using a polishing cloth till the main surface of the element formation region is exposed.
According to the manufacturing in such steps, excessive polishing of part of an element formation region is suppressed in the polishing step using a polishing cloth. As a result, the planarity of an element formation region of a semiconductor device to be manufactured is improved.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.